Typically, an integrated memory device includes a central processing unit (CPU), a memory array, I/O ports, and a controller. When data is requested, the CPU has to wait for data to come from the memory array. During this waiting period, the CPU appears to be busy, but actually it does not do anything. The speed and size of an integrated memory device are the two most critical factors in determining its performance.
In order to allow a memory device to operate at high speed, synchronous memory devices have been developed. A synchronous memory device can receive a system clock that is synchronous with the processing speed of the overall system. A modern synchronous memory system has two performance numbers. The first is latency, which is a delay between the time that a particular word is requested and the time when the memory can reliably transmit the word back to the CPU for processing. A second performance number is throughput; a rate at which a memory system can return additional data from the memory array once the latency period ends. This is often called a “burst period” because there is a burst of data transferring after the latency period. Furthermore, in new memory systems, fast synchronous data is expected out of the memory banks at clock cycle times that are far shorter than the random access capabilities of the current technologies.
Because speed and throughput are important factors in memory devices, there are many attempts to improve their performance. U.S. Pat. No. 6,560,668 B2, entitled “Method and Apparatus for Reading Write Modified Read Data in Memory Device Providing Synchronous Data Transfer” by Ryan et al., (hereinafter “the '668 Patent”) pertains to synchronous dynamic random access memory (SDRAM). The '668 patent is concerned mainly with preventing data collisions at a memory array by use of interim address and data registers that store write address and input data until an available interval is located where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. The memory device of the '668 patent juggles data and address between the interim registers and the memory array. This act is performed by arbitration circuits controlled by RAS and CAS controls. Data integrity is also checked for possibilities of data collisions. In the '668 patent, a sequence of three read commands followed by three write commands and three read commands are proposed to minimize data and address collisions. The '668 patent only teaches interim addresses to store the write addresses during read latency so that data collision can be avoided, thus improving throughput. However, the '668 patent does not teach improving of speed of the SDRAM.
Another attempt to improve speed and performance of a synchronous read only memory (RAM) is found in U.S. Pat. No. 5,610,874 by Park et al. (hereinafter “the '874 patent”). The '874 patent uses a high speed counter that uses a fast system clock to control a main decoder in burst mode. The technique in the '874 patent is a burst read without consideration to the physical limitation of read speeds due to parasitic delays and other analog sensing delays. However, the control circuits can be made fast but the ultimate data integrity is determined by proper sensing and latching of the data. Therefore, the implementation of a high speed counter to improve speed overlooks parasitic components that hinder the improvement of speed.
Neither of the above patents improved the speed of a memory device by utilizing the latency period to improve the reading speed. Furthermore, both patents require additional circuitry to avoid problems that could occur in a memory device, not performance per se. Avoiding problems that might occur means improving performance. But, the '668 patent avoid data collision problems by having interim data registers to store read commands and write commands. The '668 patent does not find a method to improve speed directly. While the '874 patent uses a fast counter to improve burst read, but it overlooks parasitic problems that worsen speed of the memory device.
Thus, there is a need to improve both throughput and speed of a memory device.